The present invention relates to semiconductor memory devices, and more particularly, to multi-level phase change memory devices.
A variety of computer memory technologies are used to store computer programs and data. Examples of the computer memory technologies include a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM). Some memory technologies need a voltage to retain stored data, while other memory technologies do not need a voltage to retain stored data.
There is an increasing demand for a nonvolatile memory that can be repetitively read and written. A typical example of the nonvolatile memory is a flash memory. The flash memory uses a floating gate transistor that retains charges on an insulated floating gate. Each memory cell of the flash memory can be electrically programmed to “1” or “0” by injecting/removing electrons into/from the floating gate. However, it is difficult to further scale down memory cells. Further, memory cells consume a relatively large amount of power, and their read/program speed is relatively slow.
Phase change memory devices have recently been proposed as nonvolatile memory devices. The phase change memory devices use materials that can be electrically changed between different structured states having different electrical read characteristics. Examples of the materials used for the phase change memory devices are chalcogenide materials such as germanium antimony tellurium (GeSbTe) compounds (hereinafter referred to as GST materials). The GST material is programmed between an amorphous state with a relatively high resistivity and a crystalline state with a relatively low resistivity. The GST material is programmed by heating. The heating intensity and heating time duration determine whether the GST material is in an amorphous or crystalline state. High and low resistivities represent programmed values “1” and “0”, which can be sensed by measuring the resistivity of the GST material.
In a typical phase change memory device, a memory cell includes a resistance element and a switching element. The switching element can be implemented using various elements such as MOS transistors and diodes. As illustrated in FIG. 1, the resistance element includes a phase change layer 1 formed of GST material, an upper electrode 2 disposed on the phase change layer 1, and a lower electrode 3 disposed on the phase change layer 1. When a pulse current is applied to the memory cell, the applied pulse current flows through the lower electrode 3. When a pulse current with a very short pulse of several ns to several tens of ns is applied to the memory cell, only a portion of the phase change layer adjacent to the lower electrode 3 is heated by joule heat. At this point, a heating profile difference changes the portion (the hatched section of FIG. 1) of the phase change layer I into a crystalline state (or a “set state”) or an amorphous state (or a “reset state”). For example, as illustrated in FIG. 2, a first pulse current i1 is applied to the memory cell and is removed within a short time of ins in order to change the phase change layer 1 into an amorphous state (or a reset state). Also, as illustrated in FIG. 2, a second pulse current i2 smaller than the first pulse current i1 is applied to the memory cell and is removed after a time period of 30˜50 ns in order to change the phase change layer 1 into a crystalline state (or a set state). Thus, the PRAM memory cell is set to one of the crystalline state and the amorphous state according to the above-described method.
Recently, in the technical field of phase change memories, efforts are being made to store M-bit data (M: an integer equal to or greater than 2), instead of 1-bit data, in one memory cell. Hereinafter, such phase change memory devices are referred to as multi-level (or multi-bit) phase change memory devices. A crystalline state and a plurality of amorphous states with different resistance values must be defined in order to store multi-level data in one memory cell. To this end, at least two resistance values (hereinafter referred to as intermediate resistance values corresponding to at least two intermediate states) must be defined between a resistance value (e.g., about 10 kΩ; hereinafter referred to as the minimum resistance value) of the memory cell with the crystalline state (or the lowest state) and another resistance value (e.g., about 1 MΩ; hereinafter referred to as the maximum resistance value) of the memory cell with the amorphous state (or the highest state). However, since the voltage range of a reset pulse for programming memory cells to have intermediate resistance values (or intermediate states) is very narrow, the intermediate resistance values (or the intermediate states) are difficult to define. This will be described in detail below.
FIG. 3 is a graph obtained by repetitively applying a set pulse and a reset pulse to memory cells while gradually increasing a pulse voltage step by step. As illustrated in FIG. 3, a set pulse and a reset pulse have the same voltage level, but a falling time of the set pulse is set to be later than a falling time of the reset pulse. The memory cell is set to the set state (corresponding to the minimum resistance value) using a set pulse with a pulse voltage of about 1.6 V, and is set to the reset state (corresponding to the maximum resistance value) using a reset pulse with a pulse voltage of about 2.0 V. As can be seen from FIG. 3, there is a small voltage margin between the set pulse voltage (e.g., about 1.6 V) and the reset pulse voltage (e.g., about 2.0 V). Therefore, it is difficult to define at least two intermediate resistance values between the minimum resistance value of the set state and the maximum resistance value of the reset state. A transition curve (e.g., the dotted section of FIG. 3) slopes steeply from the set state to the rest state. This means that it is difficult to define the resistance values corresponding to the intermediate states between the set state and the reset state. In conclusion, it is difficult to define the amorphous states having at least two intermediate resistance values between the minimum resistance value of the set state and the maximum resistance value of the reset state, by using a reset pulse illustrated in FIG. 3, i.e., a program signal having a rising time of 10 ns, a sustain time of 500 ns and a falling time of 10 ns.